1. Technical Field
The present invention relates in general to a method and computer program product for determining circuit leakage current. In particular, the present invention relates to a method and computer program product for determining the leakage current in CMOS circuit elements.
2. Description of the Related Art
Power consumption in electronic circuits has historically been a major concern and a significant design consideration. Modern designs address this concern by using CMOS (complementary-symmetry metal-oxide-semiconductor) devices in digital logic circuits. A recent trend to increase performance of these CMOS devices is to manufacture them with lower threshold voltages (lower switching voltages). These lower voltage threshold devices are termed low-Vt (LVT) devices and the regular voltage threshold devices are termed regular-Vt (RVT) devices. In order to increase CMOS logic circuit performance, low-Vt (LVT) devices have been substituted for regular-Vt (RVT) devices. In recent technologies, performance gains of approximately 30% have been seen. In past designs, entire chips or large groups of circuits used LVT devices. Unfortunately, the increased performance is offset by increased static power dissipation due to increased leakage current or (Ioff). In one CMOS process, the Ioff for an LVT device has been determined to be approximately 40 times larger than that of a RVT device. Trends in microprocessors show that the power dissipation due to leakage current will actually be higher than the power consumed by switching current in future technology generations.
In order to maximize the performance of circuits without increasing Ioff by a factor of 40, applications of LVT devices should be made judiciously. With a carefully designed library that mixes RVT and LVT devices within the same circuit, nearly all of the performance of an all LVT approach may be gained with only ⅕ to ½ of the leakage delta between the two approaches. This circuit style, termed hybrid-Vt, is used to speed up certain transitions to provide a partial speed up of all performance critical transitions.
What is needed, therefore, is a method that quickly determines circuit leakage current to assist the designer in the choice and placement of LVT and RVT devices.